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| HCF4046B MICROPOWER PHASE-LOCKED LOOP s s s s s s s s s s s s s QUIESCENT CURRENT SPECIFIED UP TO 20V VERY LOW POWER CONSUMPTION : 70W (TYP.) AT VCO fo = 10kHz, V DD = 5V OPERATING FREQUENCY RANGE : UP TO 1.4MHz (TYP.) AT VDD = 10V LOW FREQUENCY DRIFT : 0.04%/C (typ.) AT VDD = 10V CHOICE OF TWO PHASE COMPARATORS : 1) EXCLUSIVE - OR NETWORK 2) EDGE-CONTROLLED MEMORY NETWORK WITH PHASE-PULSE OUTPUT FOR LOCK INDICATION HIGH VCO LINEARITY: <1% (TYP.) VCO INHIBIT CONTROL FOR ON-OFF KEYING AND ULTRA-LOW STANDBY POWER CONSUMPTION SOURCE-FOLLOWER OUTPUT OF VCO CONTROL INPUT (demod. output) ZENER DIODE TO ASSIST SUPPLY REGULATION 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B " STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES" DIP SOP ORDER CODES PACKAGE DIP SOP TUBE HCF4046BEY HCF4046BM1 T&R HCF4046M013TR DESCRIPTION The HCF4046B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor Technology, available in 16-lead dual in-line plastic or ceramic package. The HCF4046B CMOS Micropower Phase-Locked Loop (PLL) consists of a low-power, linear voltage-controlled oscillator (VCO) and two different phase comparators having a common signal-input amplifier and a common comparator input. A 5.2V zener diode is provided for supply regulation if necessary. PIN CONNECTION September 2001 1/12 HCF4046B VCO Section The VCO requires one external capacitor C1 and one or two external resistors (R1 or R1 and R2). Resistor R1 and capacitor C1 determine the frequency range of the VCO and resistor R2 enables the VCO to have a frequency offset if required. The high input impedance (1012) of the VCO simplifiers the design of low-pass filters by permitting the designer a wide choice of resistor-to-capacitor ratios. In order not to load the low-pass filter, a source-follower output of the VCO input voltage is provided at terminal 10 (DEMODULATED OUTPUT). If this terminal is used, a load resistor (RS) of 10 K or more should be connected from this terminal to VSS. If unused this terminal should be left open. The VCO can be connected either directly or through frequency dividers to the comparator input of the phase comparators. A full CMOS logic swing is available at the output of the VCO and allows direct coupling to CMOS frequency dividers such as the HCF4024B, HCF4018B, HCF4020B, HCF4022B, HCF4029B and HBF4059A. One or more HCF4018B (Presettable Divide-by-N Counter) or HCF4029B (Presettable Up/Down Counter), or HBF4059A (Programmable Divide-by-"N" Counter), together with the HCF4046B (Phase-Locked Loop) can be used to build a micropower low-frequency synthesizer. A logic 0 on the INHIBIT input "enables" the VCO and the source follower, while a logic 1 "turns off" both to minimize stand-by power consumption. Phase Comparators The phase-comparator signal input (terminal 14) can be direct-coupled provided the signal swing is within CMOS logic levels [logic "0" 30% of (VDD-VSS), logic "1" 70% of (V DD-VSS)]. For smaller swings the signal must be capacitively coupled to the self-biasing amplifier at the signal input. Phase comparator I is an exclusive-OR network; it operates analagously to an over-driven balanced mixer. To maximize the lock range, the signal-and comparator-input frequencies must have a 50% duty cycle. With no signal or noise on the signal input, this phase comparator has an average output voltage equal to VDD/2. The low-pass filter connected to the output of phase comparator I supplies the averaged voltage to the VCO input, and causes the VCO to oscillate at the center frequency (fo). The frequency range of input signals on which the PLL will lock if it was initially out of lock is defined as the frequency capture range (2 fC). The frequency range of input signals on which the loop will stay locked if it was initially in lock is defined as the frequency lock range (2 fL). The capture range is the lock range. With phase comparator I the range of frequencies over which the PLL can acquire lock (capture range) is dependent on the low-pass-filter characteristics, and can be made as large as the lock range. Phase-comparator I enables a PLL system to remain in lock in spite of high amounts of noise in the input signal. One characteristic of this type of phase comparator is that it may lock onto input frequencies that are close to harmonics of the VCO center-frequency. A second characteristic is that the phase angle between the signal and the comparator input varies between 0 and 180, and is 90 at the center frequency. Fig.1 shows the typical, triangular, phase-to-output response characteristic of phase-comparator I. Typical waveforms for a CMOS phase-locked-loop employing phase comparator I in locked condition of fo is shown in fig.2. Phase-comparator II is an edge-controlled digital memory network. It consists of four flip-flop stages, control gating, and a three-stage output-circuit comprising p- and n-type drivers having a common output node. When the p-MOS or n-MOS drivers are ON they pull the output up to VDD or down to VSS, respectively. This type of phase comparator acts only on the positive edges of the signal and comparator inputs. The duty cycles of the signal and comparator inputs are not important since positive transitions control the PLL system utilizing this type of comparator. If the signal-input frequency is higher than the comparator-input frequency, the p-type output driver is maintained ON most of the time, and both the n- and p-drivers OFF (3 state) the remainder of the time. If the signal-input frequency is lower than the comparator-input frequency, the n-type output driver is maintained ON most of the time, and both the n- and p-drivers OFF (3 state) the remainder of the time. If the signal and comparator-input frequencies are the same, but the signal input lags the comparator input in phase, the n-type output driver is maintained ON for a time corresponding to the phase difference. If the signal and comparator-input frequencies are the same, but the comparator input lags the signal in phase, the 2/12 HCF4046B p-type output driver is maintained ON for a time corresponding to the phase difference. Subsequently, the capacitor voltage of the low-pass filter connected to this phase comparator is adjusted until the signal and comparator inputs are equal in both phase and frequency. At this stable point both p- and n-type output drivers remain OFF and thus the phase comparator output becomes an open circuit and holds the voltage on the capacitor of the low-pass filter constant. Moreover the signal at the "phase pulses" output is a high level which can be used for indicating a locked condition. Thus, for phase comparator II, no phase difference exists between signal and comparator input over the full VCO frequency range. Moreover, the power dissipation due to the low-pass filter is reduced when this type of phase comparator is used because both the pand n-type output drivers are OFF for most of the signal input cycle. It should be noted that the PLL lock range for this type of phase comparator is equal to the capture range, independent of the low-pass filter. With no signal present at the signal input, the VCO is adjusted to its lowest frequency for phase comparator II. Fig.3 shows typical waveforms for a CMOS PLL employing phase comparator II in a locked condition. Figure 1 : Phase-Comparator I Characteristics at Low-Pass Filter Output. Figure 2 : Typical Waveforms for CMOS Phase Locked-Loop Employing Phase Comparator I in Locked Condition of fo 3/12 HCF4046B Figure 3 : Typical Waveforms for CMOS Phase-locked Loop Employing Phase Comparator II In Locked Condition INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1 2 3 4 5 6, 7 9 10 11 12 13 14 15 8 16 SYMBOL PHASE PULSES PHASE COMP I OUT COMPARATOR IN VCO OUT INHIBIT C1 VCO IN DEMODULATOR OUT R1 TO VSS R2 TO VSS PHASE COMP II OUT SIGNAL IN ZENER VSS VDD NAME AND FUNCTION Phase Comparator Pulse Output Phase Comparator 1 Output Comparator Input VCO Output Inhibit Input Capacitors VCO Input Demodulator Output Resistor R1 Connection Resistor R2Connection Phase Comparator 2 Output Signal Input Diode Zener Negative Supply Voltage Positive Supply Voltage 4/12 HCF4046B FUNCTIONAL DIAGRAM ABSOLUTE MAXIMUM RATINGS Symbol VDD VI II PD Top Tstg Supply Voltage DC Input Voltage DC Input Current Power Dissipation per Package Power Dissipation per Output Transistor Operating Temperature Storage Temperature Parameter Value -0.5 to +22 -0.5 to VDD + 0.5 10 200 100 -55 to +125 -65 to +150 Unit V V mA mW mW C C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage. RECOMMENDED OPERATING CONDITIONS Symbol VDD VI Top Supply Voltage Input Voltage Operating Temperature Parameter Value 3 to 20 0 to VDD -55 to 125 Unit V V C 5/12 HCF4046B DC SPECIFICATIONS Test Condition Symbol Parameter VI (V) VO (V) |IO| VDD (A) (V) TA = 25C Min. 4.95 9.95 14.95 0.05 0.05 0.05 -3.2 -1 -2.6 -6.8 1 2.6 6.8 10-5 0.05 0.25 0.75 2 0.04 0.04 0.04 0.08 -3.2 -1 -2.6 -6.8 1 2.6 6.8 0.1 0.1 0.5 1.5 4 5 10 20 100 -1.15 -0.36 -0.9 -2.4 0.36 0.9 2.4 3.5 7 11 1.5 3 4 10-5 10-4 5 0.1 0.4 7.5 1.5 3 4 1 12 Typ. Max. Value -40 to 85C Min. 4.95 9.95 14.95 0.05 0.05 0.05 -1.15 -0.36 -0.9 -2.4 0.36 0.9 2.4 1 0.1 0.5 1.5 4 150 300 600 3000 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 3.5 7 11 1.5 3 4 1 12 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 1 0.1 0.5 1.5 4 150 300 600 Max. -55 to 125C Min. 4.95 9.95 14.95 0.05 0.05 0.05 Max. Unit VCO SECTION VOH High Level Output Voltage VOL Low Level Output Voltage Output Drive Current IOH IOL Output Sink Current 0/5 0/10 0/15 5/0 10/0 15/0 0/5 0/5 0/10 0/15 0/5 0/10 0/15 2.5 4.6 9.5 13.5 0.4 0.5 1.5 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 5 10 15 5 10 15 5 5 10 15 5 10 15 18 V V -1.36 -0.44 -1.1 -3.0 0.44 1.1 3.0 mA mA A Input Leakage 0/18 Current PHASE COMPARATOR SECTION Total Device 0/5 IDD Current 0/10 Pin 14= Open 0/15 Pin 5= VDD 0/20 0/5 Total Device Current 0/10 Pin 14= VSS or VDD 0/15 Pin 5= VDD 0/20 Output Drive 0/5 IOH Current 0/5 0/10 0/15 Output Sink 0/5 IOL Current 0/10 0/15 High Level Input VIH Voltage II VIL Low Level Input Voltage Input Leakage Current High Impedance Leakage Current Input Capacitance Any Input 2.5 4.6 9.5 13.5 0.4 0.5 1.5 0.5/4.5 1/9 1.5/13.5 4.5/0.5 9/1 13.5/1.5 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 5 10 15 20 5 10 15 20 5 5 10 15 5 10 15 5 10 15 5 10 15 18 18 mA A -1.36 -0.44 -1.1 -3.0 0.44 1.1 3.0 3.5 7 11 mA mA V V A A pF II IOUT CI 0/18 0/18 Any Input Any Input Any Input The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V 6/12 HCF4046B ELECTRICAL CHARACTERISTICS (Tamb = 25C) Test Condition Symbol Parameter VDD (V) 5 10 15 5 10 15 5 10 15 fO = 10KHz R2 = R1 = 10K R2 = R1 = 5K R2 = R1 = 10M VCOIN = VDD/2 C1 = 50pF VCOIN = VDD C1 = 50pF VCOIN = VDD 0.3 0.6 0.8 0.5 1 1.4 Min. Value (*) Unit Typ. 70 800 3000 0.6 1.2 1.6 0.8 1.4 2.4 Max. 140 1600 6000 VCO SECTION Operating Power PD Dissipation fMAX Maximum frequency W ns ns Center Frequency (fO) and frequency Range fmax - fmin Linearity 5 10 10 15 15 Temperature Frequency Stability (no frequency offset) fmin = 0 Temperature Frequency Stability (frequency offset) fmin = 0 VCO Output Duty Cycle tTLH tTHL VCO Output Transition Time Source Follower Output (Demodulated Output): Offset Voltage VCOIN-VDEM Source Follower Output (Demodulated Output): Linearity Zener Diode Voltage Zener Dynamic Resistance 5 10 15 5 10 15 5, 10, 15 5 10 15 5, 10, 15 Programable with external components R1, R2, and C1 See Design Information VCOIN =2.5V VCOIN 0.3 R1 = 10K R1 = 100K R1 = 400K R1 = 100K R1 = 1M 1.7 0.5 4 0.5 7 0.12 0.04 0.015 0.09 0.07 0.03 50 100 50 40 1.8 % 200 100 80 2.5 ns V %/C % =5V1 VCOIN =5V2.5 VCOIN =7.5V1.5 VCOIN =7.5V5 RS > 10K 5 10 15 RS = 100K RS = 300K RS = 500K IZ = 50 A IZ = 1 mA VCOIN =2.5V0.3 VCOIN =5V2.5 VCOIN =7.5V5 4.45 0.3 0.7 0.9 5.5 40 7.5 V % VZ RZ 7/12 HCF4046B Test Condition Symbol Parameter VDD (V) Min. 1 0.2 0.1 fIN = 100KHz sine wave Value (*) Unit Typ. 2 0.4 0.2 180 330 900 225 100 65 350 150 100 225 100 65 285 130 95 Max. PHASE COMPARATOR SECTION R14 Pin 14 (signal in) 5 Input Resistance 10 15 AC Coupled Signal 5 Input Sensivity (*) 10 (peak to peak) 15 Propagation Delay 5 tPLH Time High to Low 10 Level Pins 14 to 1 15 Propagation Delay 5 tPLH Time Low to High 10 Level 15 Disable Time High 5 tPHZ Level to High 10 Impedance 15 Pins 14 to 13 tPLZ Disable Time Low 5 Level to High 10 Impedance 15 Input Rise or Fall 5 tr tf Time Comparator 10 Pin 3 15 Signal Pin 14 5 10 15 5 tTLH tTHL Transition Time 10 15 M 360 660 1800 450 200 130 700 300 200 450 200 130 570 260 190 50 1 0.3 500 20 2.5 200 100 80 ns mV ns ns ns s s 100 50 40 ns (*) For sine Wave the frequency must be greater than 10KHz for Phase Comparator II 8/12 HCF4046B DESIGN INFORMATION This information is a guide for approximating the value of external components in a Phase-Locked-Loop system. The selected external components must be within the following ranges: C 1 100pF at VDD 5V C1 50pF at VDD 10V 5K R 1, R2, R S 1M USING PHASE COMPARATOR I CHARACTERISTICS VCO WITHOUT OFFSET R2= VCO WITH OFFSET USING PHASE COMPARATOR II VCO WITHOUT OFFSET R2= VCO WITH OFFSET VCO Frequency For No Signal Input Frequency Lock Range, 2fL VCO in PLL System will Adjust to Centre Frequency fo VCO in PLL System will Adjust to Lowest Operating Frequency fo 2 fL = Full VCO Frequency Range 2fL = fmax - fmin Frequency Lock Range, 2fC fC = fL Loop filter Component Section Phase Angle Between SIgnal and Comparator Locks on Harmonics of Centre Frequency Signal Input Nose Rejection 90 at Centre frequency (fO), approximating 0 and 180 at ends of lock range (2 fL) Yes High Always 0 in lock No Low For further information, see (1) F. Gardner, "Phase-Lock Techniques" John Wiley and Sons, New York, 1966 (2) G.S. Mosckytz "miniaturized RC filters using phase Lockedloop" BSTJ May 1965 9/12 HCF4046B Plastic DIP-16 (0.25) MECHANICAL DATA mm. DIM. MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.27 8.5 2.54 17.78 7.1 5.1 0.130 0.050 0.51 0.77 0.5 0.25 20 0.335 0.100 0.700 0.280 0.201 1.65 TYP MAX. MIN. 0.020 0.030 0.020 0.010 0.787 0.065 TYP. MAX. inch P001C 10/12 HCF4046B SO-16 MECHANICAL DATA DIM. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 9.8 5.8 1.27 8.89 4.0 5.3 1.27 0.62 8 (max.) 0.149 0.181 0.019 10 6.2 0.35 0.19 0.5 45 (typ.) 0.385 0.228 0.050 0.350 0.157 0.208 0.050 0.024 0.393 0.244 0.1 mm. MIN. TYP MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.003 MIN. inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010 PO13H 11/12 HCF4046B Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2001 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom (c) http://www.st.com 12/12 |
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